Comparative Study of PLL, DDS and DDS-based PLL Synthesis Techniques for Communication System

The phase locked loop(PLL) has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. The Direct Digital Synthesis(DDS) is also an emerging and maturing signal generation technology. But another advanced technique in which, DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. The proposed design consists in describing the mixed behavior of this DDS-based PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the system performance. The obtained results are composed with transistor-level simulations to validate the effectiveness of the proposed models. The comparative study showed the performances of different parameters. Finally, DDSbased PLL architecture is better than other architectures.